A typical physical structure of a p-n diode is shown in Figure 4.2.1a. It consists of a heavily p-type doped region in a lower doped n-type epitaxial layer on an n-type substrate. The p-type region can be created by diffusion or implantation of p-type dopants, for instance boron in the case of a silicon diode. A metal contact is made to both sides of the substrate, forming the anode on the p-type side and the cathode on the n-type side. The diode die is soldered to the package and a wire bond is used to contact the anode on the front of the die. The p-n diode operation takes place in the region around the p-n metallurgical interface, indicated with the dashed box on the figure. This region is presented in more detail in Figure 4.2.1b. The region on the left is p-type with an acceptor density N_a, while the region on the right is n-type with a donor density Nd. The dopants are assumed to be shallow, so that the electron (hole) density in the n-type (p-type) region is approximately equal to the donor (acceptor) density. The circuit symbol is shown in Figure 4.2.1c.

We will assume, unless stated otherwise, that the doped regions are uniformly doped and that the transition between the two regions is abrupt. We will refer to this structure as an abrupt p-n junction.

Often, we will deal with p-n junctions where one side is distinctly higher-doped than the other. In such case only the low-doped region needs to be considered, since it primarily determines the device characteristics. We will refer to such a structure as a one-sided abrupt p-n junction.

The junction is biased with a voltage V_a as shown in Figure 4.2.1. We will call the junction forward-biased if a positive voltage is applied to the p-doped region and reversed-biased if a negative voltage is applied to the p-doped region. The contact to the p-type region is also called the anode, while the contact to the n-type region is called the cathode, in reference to the anions or positive carriers and cations or negative carriers in each of these regions.

4.2.1. Flatband diagram

The principle of operation will be explained using a gedanken experiment, an experiment, which is in principle possible but not necessarily executable in practice. We imagine that one can bring both semiconductor regions together, aligning both the conduction and valence band energies of each region. This yields the so-called flatband diagram shown in Figure 4.2.2.

Note that this does not automatically align the Fermi energies, E_F,n and E_F,p. Also, note that this flatband diagram is not an equilibrium diagram since both electrons and holes can lower their energy by crossing the junction. A motion of electrons and holes is therefore expected before thermal equilibrium is obtained. The diagram shown in Figure 4.2.2 (b) is called a flatband diagram. This name refers to the horizontal band edges. It also implies that there is no field and no net charge in the semiconductor.

4.2.2. Thermal equilibrium

To reach thermal equilibrium, electrons/holes close to the metallurgical junction diffuse across the junction into the p-type/n-type region where hardly any electrons/holes are present. This process leaves the ionized donors (acceptors) behind, creating a region around the junction, which is depleted of mobile carriers. We call this region the depletion region, extending from x = -x_p to x = x_n. The charge due to the ionized donors and acceptors causes an electric field, which in turn causes a drift of carriers in the opposite direction. The diffusion of carriers continues until the drift current balances the diffusion current, thereby reaching thermal equilibrium as indicated by a constant Fermi energy. This situation is shown in Figure 4.2.3:

While in thermal equilibrium no external voltage is applied between the n-type and p-type material, there is an internal potential, φ_i, which is caused by the workfunction difference between the n-type and p-type semiconductors. This potential equals the built-in potential, which will be further discussed in the next section.

4.2.3. The built-in potential

The built-in potential in a semiconductor equals the potential across the depletion region in thermal equilibrium. Since thermal equilibrium implies that the Fermi energy is constant throughout the p-n diode, the built-in potential equals the difference between the Fermi energies, E_Fn and E_Fp, divided by the electronic charge. It also equals the sum of the bulk potentials of each region, φ_n and φ_p, since the bulk potential quantifies the distance between the Fermi energy and the intrinsic energy.

where the subscripts indicate the material type. This yields the following expression for the built-in potential.

1. Calculate the thermal equilibrium density of electrons and holes in the p-type region as well as both densities in the n-type region.
2. Calculate the built-in potential of the p-n junction
3. Calculate the built-in potential of the p-n junction at 400 K.

1. The thermal equilibrium densities are:
   In the p-type region:p = N_a = 2 x 10¹⁶ cm^-3
   n = n_i²/p = 10²⁰/2 x 10¹⁶ = 5 x 10³ cm^-3In the n-type regionn = N_d - N_a = 9 x 10¹⁶ cm^-3
   p = n_i2/n = 10²⁰/(1 x 10¹⁶) = 1.11 x 10³ cm^-3
2. The built-in potential is obtained from:

   

3. Similarly, the built-in potential at 400 K equals:

   

   where the instrinsic carrier density at 400 K was obtained from example 2.4.b

4.2.4. Forward and reverse bias

We now consider a p-n diode with an applied bias voltage, V_a. A forward bias corresponds to applying a positive voltage to the anode (the p-type region) relative to the cathode (the n-type region). A reverse bias corresponds to a negative voltage applied to the cathode. Both bias modes are illustrated with Figure 4.2.4. The applied voltage is proportional to the difference between the Fermi energy in the n-type and p-type quasi-neutral regions.

As a negative voltage is applied, the potential across the semiconductor increases and so does the depletion layer width. As a positive voltage is applied, the potential across the semiconductor decreases and with it the depletion layer width. The total potential across the semiconductor equals the built-in potential minus the applied voltage, or:

Boulder, November 2007